`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    22:42:57 04/04/2013 
// Design Name: 
// Module Name:    dff 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////

// dff implementation that resets the output to 1 rather than 0
//
module ndff(
    input data,
    input clk,
    input reset,
    output q
    );

reg opq;

always@(posedge clk or negedge reset)
	if (!reset)
		opq = 1'b1;
	else
		opq = data;

assign q = opq;

endmodule


module dff(
    input data,
    input clk,
    input reset,
    output q
    );

reg opq;

always@(posedge clk or negedge reset)
	if (!reset)
		opq = 1'b0;
	else
		opq = data;

assign q = opq;

endmodule
